1. Field of the Invention
The invention generally relates to integrated circuits and in particular to CMOS bias circuits for biasing operational amplifiers of switched capacitor (SC) circuits or other devices employing NMOS or PMOS differential pairs.
2. Description of the Related Art
Operational amplifiers containing differential pairs are commonly employed within integrated circuits as components of, for example, SC analog signal processing circuits. Bias circuits are employed in connection with the differential pairs of the operational amplifiers to ensure that certain characteristics of the operational amplifier remain substantially constant despite temperature changes or process variations. Examples include bias circuits for maintaining a constant current or a constant transconductance (gm) within the differential pair of the operational amplifier. A constant gm is more efficient than constant current. For operational amplifiers used in SC circuits, the operational speed of the SC circuit is limited primarily by the unity gain bandwidth of the operational amplifiers. More specifically, the settling time of the SC circuit is a strong function of the unity gain bandwidth of the operational amplifiers wherein the unity gain bandwidth is given by             ω      0        =                  g        m                    C        L              ,
where gm is the transconductance of the operational amplifier and CL is the effective load capacitance.
Hence, bias circuits providing only a constant gm do not necessarily yield improved performance speed for SC circuits. Rather, a bias circuit providing a constant gm/CL is preferred. In the following, various conventional bias circuits for use with operational amplifiers are described and unity gain bandwidth issues arising with respect to the bias circuits are discussed.
FIG. 1 illustrates an exemplary operational amplifier 10 appropriate for use in a SC circuit. Operational amplifier 10 includes a differential pair of NMOS devices 12 and 14 and a differential pair of PMOS current mirror devices 13 and 15. The four devices are interconnected, as shown, between a positive voltage source VDD and a node A. The pair of NMOS devices have gates connected to a pair of voltage input lines 16 and 18, respectively. An output line 20 is connected to a node interconnecting NMOS device 14 and PMOS device 15 as shown. A capacitor 21, providing a load capacitance of CL, couples the output signal to an external load 22. To ensure that certain circuit characteristics such as current or gm remain constant despite temperature or process variations, the operational amplifier is biased by a bias signal provided along. a bias line 25 and applied to the gate of an additional NMOS device 24 connected between node A and ground.
FIG. 2 illustrates operational amplifier 10 of FIG. 1 in combination with a bias circuit 26 for maintaining constant current despite temperature changes and process variations. Bias circuit 26 includes a current source 27 in combination with a single NMOS device 29 configured to operate as a current mirror. With this arrangement, the operational amplifier is biased to maintain constant current proportional to the current provided by current source 27, independent of temperature changes and process variations.
However, the gm of the operational amplifier is not maintained as a constant. Rather the gm of the operational amplifier of FIG. 2 is given by:             g      m        =                  2        ⁢                  I          0                                      v          GS                -                  V          T                      ,
where, I0 is the bias current, VGS is the gate to source voltage of device 12, and VT is the threshold of device 12. VT changes with temperature and process variations. Thus gm varies due to temperature and process fluctuations. Moreover, for most applications, the load capacitance (CL) also changes due to process variations by about xc2x110%. Therefore, the unity gain bandwidth of an operational amplifier biased with a constant current source can change significantly due to gm and CL variations caused by temperature changes and process fluctuations. Hence, the speed performance of an SC circuit employing the operational amplifier is degraded.
FIG. 3 illustrates operational amplifier 10 of FIG. 1 in combination with a bias circuit 30 for maintaining a constant gm despite temperature changes and process variations. Briefly, the bias circuit includes a pair of NMOS devices 32 and 34 connected between a pair of nodes B and C and ground, respectively. A pair of PMOS devices 33 and 35 are connected, respectively, between nodes B and C and a positive voltage source. Gates of NMOS devices 32 and 34 are connected to node B. Gates of PMOS devices 33 and 35 are connected to node C. A gm-setting resistor 36 is connected between the source of NMOS device 34 and ground. Resistor 36 is typically located off-chip to permit the resistance to be set after chip fabrication. In use, bias circuit 30 operates as a current mirror to generate a bias current that sets the gm""s of NMOS devices 12 and 14 of the operational amplifier to an amount inversely proportional to the resistance of gm-setting resistor 36. The bias circuit is, in effect, an MOS version of a self-biasing Widlar current source, well known in the art.
Thus, the bias circuit of FIG. 3 substantially guarantees that the gm of the operational amplifier does not vary due to process and temperature variations, at least to the first order. More specifically, the Kirchoff voltage levels for the circuit are given by:
I0R+xcexdGS2=xcexdGS1.
Assuming a quadratic equation for the drain saturation current:             v      GS        -          v      T        =                              (          Id          )                /                  (                                    1              2                        ⁢            μ            ⁢                          xe2x80x83                        ⁢                          C              OX                        ⁢                          W              L                                )                      .  
If threshold voltages of devices 32 and 34 of the bias circuit are assumed to be equal (ignoring body effects) then:
xcexdGS1xe2x88x92VT=2(xcexdGSxe2x88x92VT)
Hence:
I0R=xc2xd(VGS1xe2x88x92VT)
and thus,       g    m    =                    2        ⁢                  I          0                                      v          GS1                -                  V          T                      =                  1        R            .      
Thus, disregarding body effects, the gm""s of the devices of the operational amplifier are merely proportional to the resistance of gm-setting resistor 36. Unfortunately, in practical integrated circuits, body effects can pose a significant problem. Briefly, body effects relate to a modification of the threshold voltage VT caused by a voltage difference between source and substrate. The change in voltage threshold is proportional to the square root of the voltage between the source and the substrate.
In the circuit of FIG. 3, the change in threshold voltage results in two separate problems. The first problem occurs from the variations in source voltage between NMOS devices 32 and 34 of the bias circuitry. Since the source of NMOS device 34 is at a different voltage from that of device 32, the gm is not merely proportional to the resistance of resistor 36 but is instead given by the following equation:       g    m    =            1      +                        1          +                      2            ·            B            ·            R            ·            vterr                                      2      ⁢      R      
where   B  =            μ      n        ⁢    Cox    ⁢                  W        L            .      
This formula for gm may be derived from the following set of equations:
xcexdgs1=xcexdgs2+Ixc2x7Rxe2x88x92xcexdterr
and since   vgs  =                    2        ·                  I          B                      -          v      T0      
with   B  =            μ      n        ⁢    Cox    ⁢                  W        L            .      
then             2      ·              I        B              =                    1        2            ⁢                        2          ·                      I            B                                +          I      ·      R        -          vterr      .      
solving for       I    =                    1                              2            ·            B                              +                                    2            B                    +                      R            ·            vterr                                      2      ⁢      R      
yields
gm={square root over (2+L xc2x7Bxc2x7I)}
and finally       g    m    =                    1        +                              1            +                          2              ·              B              ·              R              ·              vterr                                                  2        ⁢        R              .  
The second body effect problem occurs as a result of absolute differences between devices 32 and 34 of the bias circuitry and devices 12 and 14 of the operational amplifier. The absolute current generated in the bias circuit is proportional to the threshold voltage, and therefore any variances between the source voltages will result in a different gm value. Since the input common mode voltage to the operational amplifier is fixed, the source voltage of devices 12 and 14 will vary with process causing a non-tracking gm. As a result, temperature changes and process variations are not fully compensated for by the CMOS bias circuitry of FIG. 1 resulting in variations in the gm of the operational amplifier. Hence, the unity gain bandwidth is again affected.
Co-pending U.S. patent application Ser. No. 09/283090, filed Mar. 31, 1999 describes an improved constant gm bias circuit which compensates for variations caused by body effects in addition to variations caused by temperature or process to provide a constant gm. The co-pending application is entitled xe2x80x9cConstant Transconductance Bias Circuit having Body Effect Cancellation Circuitryxe2x80x9d of Jeremy Goldblatt and Seyfi Bazarjani. The co-pending application is incorporated by reference herein. However, as noted above, the speed performance of an SC circuit incorporating operational amplifiers is limited by the unity gain bandwidth of the operational amplifiers. Even with a bias circuit that provides constant gm, the unity gain bandwidth may still vary as a result of changes in the load capacitance (CL) of the bias circuit. Hence, it would be highly desirable to provide an improved bias circuit for use with operational amplifiers, or other devices employing an NMOS differential pair, that maintains a substantially constant gm/CL despite temperature and process variations and also despite body effects and it is to that end that aspects of the invention are primarily directed.
In accordance with a first aspect of the invention, a bias circuit is provided for use in biasing a differential pair, such as an NMOS differential pair of an operational amplifier, to maintain a constant gm/CL despite temperature and process variations. The bias circuit includes a pair of current source devices and a resistance equivalent circuit for developing an equivalent resistance between the current source devices. The resistance equivalent circuit includes a sampling capacitor connected between a sampling node connecting the pair of current source devices and a ground. A first clock input is connected between the sampling node and a first current source device and a second clock input is connected between the sampling node and a second current source device. The first and second clock inputs provide non-overlapping clock signals at a predetermined sampling frequency to establish a resistance equivalent. Voltage-setting circuitry is connected to the resistance equivalent circuit for applying a voltage across the circuit to cause the bias circuit to generate a bias signal. A bias line transmits the bias signal to the differential pair being biased.
By providing the bias circuit as described with a resistance equivalent circuit with non-overlapping clock signals at a predetermined frequency, the gm/CL of the bias circuit is maintained substantially constant to thereby maintain a fixed bandwidth within the differential pair being biased. When employed in connection with operational amplifiers of an SC circuit, the constant bandwidth enables the SC circuit to operate at a constant switching speed in independent of temperature and process variations.
Furthermore, by positioning the resistance equivalent circuit between the current source devices of the bias circuit, voltage differentials between the source-drain of MOSFETs are eliminated thereby removing any threshold voltage mismatch. Hence, body effect variations that will affect the threshold voltage do not cause a significant change in the gm/CL of the bias circuit. Source follower circuitry may also be provided to substantially eliminate any absolute differences between the source terminals of the current source devices of the bias circuit and sources of the differential pair thereby further reducing variations in gm/CL caused by body effects.
In accordance with a second aspect of the invention, a stray insensitive bias circuit for use in biasing a differential pair is provided wherein a substantially constant gm/CL is maintained and a bandwidth center frequency of the bias circuit does not drift. The bias circuit includes a pair of current source devices and a resistance equivalent circuit for developing an equivalent resistance between the current source devices. The equivalent circuit includes a capacitor connected between gates of first and second current source devices. A first clock input is connected between a first terminal of the capacitor and the gate of the first current source device and is also connected between a second terminal of the capacitor and the gate of the second current source device. A second clock input is connected between the first terminal of the capacitor and a ground and also connected between the second terminal of the capacitor and the ground. The first and second clock inputs provide non-overlapping clock signals at a predetermined sampling frequency to establish a resistance equivalent.
By providing two sets of clock signal inputs connected to the capacitor as described, a constant gm/CL is maintained without significant drift. Voltage differentials between the source terminals of the current sources are also eliminated to thereby compensate for body effect variations. As with the first aspect of the invention, a pair of resistance equivalent circuits may be employed in parallel instead of just one to help eliminate parasitic capacitance effects that might otherwise affect the constant gm/CL bias. Source follower circuitry may also be provided to substantially eliminate any absolute differences between the sources of the current source devices of the bias circuit and sources of the differential pair thereby further reducing variations in gm/CL caused by body effects.
In accordance with a third aspect of the invention, another bias circuit for use in biasing a differential pair is provided to maintain a substantially constant gm/CL. The bias circuit includes a pair of current source devices and a capacitor. A first clock input is connected between a first terminal of the capacitor and a current output line output from the differential pair being biased. The first clock input is also connected between a second terminal of the capacitor and a common mode voltage input line. A second clock input is connected between the first terminal of the capacitor and a positive voltage reference line and is also connected between the second terminal of said capacitor and a negative voltage reference line. A third clock input is connected between the first terminal of said capacitor and a ground and also connected between the second terminal of said capacitor and said ground. The first, second and third clock inputs provide mutually non-overlapping clock signals at a predetermined sampling frequency to establish a resistance equivalent.
By providing three sets of clock signal inputs connected to the switching capacitor as described, a constant gm/CL is maintained without significant drift and variations that might otherwise be caused by parasitic capacitances are substantially avoided. Source follower circuitry may also be provided to substantially eliminate any absolute differences between the sources of the current source devices of the bias circuit and sources of the differential pair thereby further reducing variations in gm/CL caused by body effects.
Method and apparatus embodiments of the invention are provided.